First-in first--out memories (FIFOs) are well known in the art. A typical prior art FIFO memory is disclosed in U.S. Pat. No. 4,151,609 issued to Moss in Apr. 24, 1979. FIFOs are similar to shift registers in that data entered at the input appear at the output in the same order. However, in a FIFO if the output queue is empty, data just entered will be available almost immediately. A typical application for a FIFO is to buffer an input device to a slower data-computation device. In this manner, no data are lost if the device is not ready for each input as it is generated, assuming the FIFO has not filled up completely. However, in the case that the FIFO is completely full, the input device must be halted, thereby decreasing performance. Increasing the depth of the FIFO to solve this problem results in a much larger register and additional control logic, both of which undesirably increase the size of the device.